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256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM
DDR SDRAM Unbuffered Module
184pin Unbuffered Module based on 512Mb B-die
66 TSOP-II & 54 sTSOP-II
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Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
Table of Contents
DDR SDRAM
1.0 Ordering Information................................................................................................................... 4 2.0 Operating Frequencies................................................................................................................ 4 3.0 Feature.......................................................................................................................................... 4 4.0 Pin Configuration (Front side/back side) ................................................................................. 5 5.0 Pin Description ............................................................................................................................ 5 6.0 Functional Block Diagram .......................................................................................................... 6 6.1 256MB, 32M x 64 Non ECC Module (M470L3324BT(U)0) .................................................................... 6
6.2 512MB, 64M x 64 Non ECC Module (M470L6524BT(U)0) ..................................................................................7 6.3 1GB, 128M x 64 Non ECC Module (M470L2923BN(V)0) ...................................................................... 8
7.0 Absolute Maximum Ratings........................................................................................................ 9 8.0 DC Operating Conditions............................................................................................................ 9 9.0 DDR SDRAM IDD spec table ..................................................................................................... 10 9.1 M470L3324BT(U)0 [ (32M x 16) * 4, 256MB Non ECC Module ]............................................................................. 10 9.2 M470L6524BT(U)0 [ (32M x 16) * 8, 512MB Non ECC Module ]............................................................................. 10 9.3 M470L2923BN(V)0 [ (64M x 8) * 16, 1GB Non ECC Module ] ................................................................................. 11 10.0 AC Operating Conditions........................................................................................................ 12 11.0 Input/Output Capacitance ....................................................................................................... 12 12.0 AC Timming Parameters & Specifications ............................................................................ 13 13.0 System Characteristics for DDR SDRAM .............................................................................. 14 14.0 Component Notes.................................................................................................................... 15 15.0 System Notes ........................................................................................................................... 16 16.0 Command Truth Table............................................................................................................. 17 17.0 Physical Dimensions............................................................................................................... 18 17.1 32Mx64 (M470L3324BT(U)0) ..................................................................................................... 18 17.2 64Mx64 (M470L6524BT(U)0) ..................................................................................................... 19 17.3 128Mx64 (M470L2923BN(V)0) ................................................................................................... 20
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
Revision History
Revision 1.0 1.1 1.2 1.3 1.4 1.5 Month February June July October March June Year 2003 2003 2003 2003 2004 2005 - First release - Updated DC characteristics. - Corrected Pin configuration table. - Corrected typo in physical module dimenstion - Corrected package dimension. - Changed master format History
DDR SDRAM
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM
200Pin Unbuffered SODIMM based on 512Mb B-die (x8, x16) 1.0 Ordering Information
Part Number M470L3324BT(U)0-C(L)CC/B3/A2/B0 M470L6524BT(U)0-C(L)CC/B3/A2/B0 M470L2923BN(V)0-C(L)CC/B3/A2/B0 Density 256MB 512MB 1GB Organization 32M x 64 64M x 64 128M x 64 Component Composition 32Mx16 (K4H511638B) * 4EA 32Mx16 (K4H511638B) * 8EA 64Mx8 (K4H510838B) * 16EA Height 1,250mil 1,250mil 1,250mil
Note : Leaded and Lead-free(Pb-free) can be discriminated by PKG P/N (T : 66 TSOP with Leaded, U : 66 TSOP with Lead-free) (N : 54 sTSOP with Leaded, V : 54 sTSOP with Lead-free)
2.0 Operating Frequencies
CC(DDR400@CL=3) Speed @CL2 Speed @CL2.5 Speed @CL3 CL-tRCD-tRP 166MHz 200MHz 3-3-3 B3(DDR333@CL=2.5) 133MHz 166MHz 2.5-3-3 A2(DDR266@CL=2) 133MHz 133MHz 2-3-3 B0(DDR266@CL=2.5) 100MHz 133MHz 2.5-3-3
3.0 Feature
* VDD : 2.5V 0.2V, VDDQ : 2.5V 0.2V for DDR266, 333 * VDD : 2.6V 0.1V, VDDQ : 2.6V 0.1V for DDR400 * Double-data-rate architecture; two data transfers per clock cycle * Bidirectional data strobe [DQ] (x4,x8) & [L(U)DQS] (x16) * Differential clock inputs(CK and CK) * DLL aligns DQ and DQS transition with CK transition * Programmable Read latency : DDR266(2, 2.5 Clock), DDR333(2.5 Clock), DDR400(3 Clock) * Programmable Burst length (2, 4, 8) * Programmable Burst type (sequential & interleave) * Edge aligned data output, center aligned data input * Auto & Self refresh, 7.8us refresh interval(8K/64ms refresh) * Serial presence detect with EEPROM * PCB : Height - 256MB(non ECC/ECC SS, 1250mil), 512MB/1GB(non ECC DS, 1250mil, ECC DS, 1400mil) * SSTL_2 Interface * 66pin TSOP II & 54pin sTSOP II (Leaded & Pb-Free(RoHS compliant)) package
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
4.0 Pin Configuration (Front side/back side)
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 KEY DQ16 DQ17 VDD DQS2 DQ18 VSS DQ19 DQ24 VDD DQ25 DQS3 VSS DQ26 Front VREF VSS DQ0 DQ1 VDD DQS0 DQ2 VSS DQ3 DQ8 VDD DQ9 DQS1 VSS DQ10 DQ11 VDD CK0 CK0 VSS Pin 67 69 71 73 75 77 79 81 83 85 87 89 91 93 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 Front DQ27 VDD CB0 CB1 VSS DQS8 CB2 VDD CB3 DU VSS CK2 CK2 VDD CKE1 DU A12 A9 VSS A7 A5 A3 A1 VDD A10/AP BA0 WE CS0 *DU(A13) VSS DQ32 DQ33 VDD DQS4 Pin 135 137 139 141 143 145 147 149 151 153 155 157 159 161 163 165 167 169 171 173 175 177 179 181 183 185 187 189 191 193 195 197 199 Front DQ34 VSS DQ35 DQ40 VDD DQ41 DQS5 VSS DQ42 DQ43 VDD VDD VSS VSS DQ48 DQ49 VDD DQS6 DQ50 VSS DQ51 DQ56 VDD DQ57 DQS7 VSS DQ58 DQ59 VDD SDA SCL VDDSPD VDDID 42 44 46 48 50 52 54 56 58 60 62 64 66 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 Back VREF VSS DQ4 DQ5 VDD DM0 DQ6 VSS DQ7 DQ12 VDD DQ13 DM1 VSS DQ14 DQ15 VDD VDD VSS VSS KEY DQ20 DQ21 VDD DM2 DQ22 VSS DQ23 DQ28 VDD DQ29 DM3 VSS DQ30 Pin 68 70 72 74 76 78 80 82 84 86 88 90 92 94 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 Back DQ31 VDD CB4 CB5 VSS DM8 CB6 VDD CB7
DDR SDRAM
Pin 136 138 140 142 144 146 148 150 152 154 156 158 160 162 164 166 168 170 172 174 176 178 180 182 184 186 188 190 192 194 196 198 200 Back DQ38 VSS DQ39 DQ44 VDD DQ45 DM5 VSS DQ46 DQ47 VDD CK1 CK1 VSS DQ52 DQ53 VDD DM6 DQ54 VSS DQ55 DQ60 VDD DQ61 DM7 VSS DQ62 DQ63 VDD SA0 SA1 SA2 DU
*DU/(RESET) VSS VSS VDD VDD CKE0 *DU(BA2) A11 A8 VSS A6 A4 A2 A0 VDD BA1 RAS CAS CS1 DU VSS DQ36 DQ37 VDD DM4
Note : 1. * : These pins are not used in this module. 2. Pins 71, 72, 73, 74, 77, 78, 79, 80, 83, 84 are not used on x64(M470~ ) module, & used on x72(M485 ~ ) module. 3. Pins 95,122 are NC for 1Row module & used for 2Row moule(M470L6524B).
5.0 Pin Description
Pin Name A0 ~ A12 BA0 ~ BA1A DQ0 ~ DQ63 DQS0 ~ DQS8 CK0,CK0 ~ CK2, CK2 CKE0, CKE1(for double banks) CS0, CS1(for double banks) RAS CAS WE CB0 ~ CB7(for x72 module) Function Address input (Multiplexed) Bank Select Address Data input/output Data Strobe input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Write enable Check bit(Data-in/data-out) Pin Name DM0 ~7,8(for ECC) Data - in mask VDD VDDQ VSS VREF VDDSPD SDA SCL SA0 ~ 2 VDDID NC Power supply (2.5V for DDR266/333, 2.6V for DDR400) Power Supply for DQS (2.5V for DDR266/333, 2.6V for DDR400) Ground Power supply for reference Serial EEPROM Power/Supply ( 2.3V to 3.6V ) Serial data I/O Serial clock Address in EEPROM VDD, VDDQ level detection No connection Function
Note : VDDID defines relationship of VDD and VDDQ, and the default status of it is open (VDD=VDDQ)
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
6.0 Functional Block Diagram
6.1 256MB, 32M x 64 Non ECC Module (M470L3324BT(U)0)
(Populated as 1 bank of x16 DDR SDRAM Module)
CS0 DQS0 DM0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQS1 DM1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 CS DQS4 DM4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQS5 DM5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7 CS
DDR SDRAM
D0
D2
DQS2 DM2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQS3 DM3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7
CS
D1
DQS6 DM6 DQ 48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 DQS7 DM7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 8 I/0 9 I/0 10 I/0 11 UDQS UDM I/0 3 I/0 2 I/0 1 I/0 0 I/0 4 I/0 5 I/0 6 I/0 7
CS
D3
BA0 - BA1 A0 - A12 RAS CAS CKE0 WE
BA0-BA1: DDR SDRAMs D0 - D3 A0-A12: DDR SDRAMs D0 - D3 RAS: SDRAMs D0 - D3
Cap/Cap/Cap D0/D2/Cap
CAS: SDRAMs D0 - D3 CKE: SDRAMs D0 - D3 WE: SDRAMs D0 - D3 Clock Input CK0/CK0 CK1/CK1 CK2/CK2
Clock Wiring SDRAMs 2 SDRAMs 2 SDRAMs NC
CK0/1/2 CK0/1/2 Card Edge
R=120 5%
D1/D3/Cap
VDDSPD VDD/VDDQ
Cap/Cap/Cap
SPD D0 - D3 D0 - D3 Serial PD SCL WP A0 SA0 A1 SA1 A2 SA2
VREF VSS
D0 - D3 D0 - D3
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must SDA be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
6.2 512MB, 64M x 64 Non ECC Module (M470L6524BT(U)0)
(Populated as 2 bank of x16 DDR SDRAM Module)
DDR SDRAM
CS1 CS0 DQS0 DM0 DQ 0 DQ 1 DQ 2 DQ 3 DQ 4 DQ 5 DQ 6 DQ 7 DQS1 DM1 DQ 8 DQ 9 DQ 10 DQ 11 DQ 12 DQ 13 DQ 14 DQ 15 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 11 I/0 10 I/0 9 I/0 8 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0 CS LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 CS DQS4 DM4 DQ 32 DQ 33 DQ 34 DQ 35 DQ 36 DQ 37 DQ 38 DQ 39 DQS5 DM5 DQ 40 DQ 41 DQ 42 DQ 43 DQ 44 DQ 45 DQ 46 DQ 47 LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 11 I/0 10 I/0 9 I/0 8 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0 CS LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15 CS
D0
D4
D2
D6
DQS2 DM2 DQ 16 DQ 17 DQ 18 DQ 19 DQ 20 DQ 21 DQ 22 DQ 23 DQS3 DM3 DQ 24 DQ 25 DQ 26 DQ 27 DQ 28 DQ 29 DQ 30 DQ 31
LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 11 I/0 10 I/0 9 I/0 8 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0
CS
D1
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
CS
D5
DQS6 DM6 DQ48 DQ 49 DQ 50 DQ 51 DQ 52 DQ 53 DQ 54 DQ 55 DQS7 DM7 DQ 56 DQ 57 DQ 58 DQ 59 DQ 60 DQ 61 DQ 62 DQ 63
LDQS LDM I/0 15 I/0 14 I/0 13 I/0 12 I/0 11 I/0 10 I/0 9 I/0 8 UDQS UDM I/0 7 I/0 6 I/0 5 I/0 4 I/0 3 I/0 2 I/0 1 I/0 0
CS
D3
LDQS LDM I/0 0 I/0 1 I/0 2 I/0 3 I/0 4 I/0 5 I/0 6 I/0 7 UDQS UDM I/0 8 I/0 9 I/0 10 I/0 11 I/0 12 I/0 13 I/0 14 I/0 15
CS
D7
*Clock Net Wiring
D0/D2/Cap
BA0 - BA1 A0 - A12 RAS CAS CKE0 CKE1 WE VDDSPD VDD/VDDQ
BA0-BA1: DDR SDRAMs D0 - D7 A0-A12: DDR SDRAMs D0 - D7 RAS: SDRAMs D0 - D7 CAS: SDRAMs D0 - D7 CKE: SDRAMs D0 - D3 CKE: SDRAMs D4 - D7 WE: SDRAMs D0 - D7 SPD D0 - D7 SCL WP SDA A0 SA0 A1 SA1 A2 SA2
D5/D7/Cap
Clock Wiring Clock Input CK0/CK0 CK1/CK1 CK2/CK2 SDRAMs 4 SDRAMs 4 SDRAMs NC CK0/1/2 CK0/1/2 Card Edge
R=120
D1/D3/Cap
D4/D6/Cap
Serial PD
VREF VSS
D0 - D7 D0 - D7
Notes: 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown. 3. DQ, DQS, DM/DQS resistors: 22 Ohms.
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
6.3 1GB, 128M x 64 Non ECC Module (M470L2923BN(V)0)
(Populated as 2 bank of x8 DDR SDRAM Module)
DDR SDRAM
CS1 CS0 DQS0 DM0 DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQS1 DM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQS2 DM2 DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQS3 DM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQS7 DM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DQS4 DM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 DQS5 DM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQS6 DM6 DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS DM I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 CS DQS
D0
D8
D4
D12
D1
D9
D5
D13
D2
D10
D6
D14
D3
D11
D7
D15
BA0 - BA1 A0 - A12 RAS CAS CKE1 CKE0 WE
BA0-BA1: DDR SDRAMs D0 - D15 A0-A12 : DDR SDRAMs D0 - D15 RAS CAS CKE CKE WE : DDR SDRAMs D0 - D15 : DDR SDRAMs D0 - D15 : DDR SDRAMs D8 - D15 : DDR SDRAMs D0 - D7 : DDR SDRAMs D0 - D15 CK0 / 1 CK0 / 1 Card Edge R=120 5%
D0,D8 / D4,D12 D1,D9 / D5,D13 D2,D10/ D6,D14 D3,D11/ D7,D15 *Clock Net Wiring
CK2 10pF CK2
VDDSPD VDD/VDDQ
SPD D0 - D15 D0 - D15 Notes : 1. DQ-to-I/O wiring is shown as recommended but may be changed. 2. DQ/DQS/DM/CKE/CS relationships must be maintained as shown 3. DQ, DQS, DM/DQS resistors: 22 Ohm.
VREF VSS
D0 - D15 D0 - D15
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
7.0 Absolute Maximum Ratings
Parameter Voltage on any pin relative to VSS Voltage on VDD & VDDQ supply relative to VSS Storage temperature Power dissipation Short circuit current Symbol VIN,VOUT VDD,VDDQ TSTG PD IOS Value -0.5 ~ 3.6 -1.0 ~ 3.6 -55 ~ +150
DDR SDRAM
Unit V V C W mA
1.5 * # of component 50
Note : Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
8.0 DC Operating Conditions
Recommended operating conditions(Voltage referenced to VSS=0V, TA=0 to 70C)
Parameter
Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) Supply voltage(for device with a nominal VDD of 2.6V for DDR400) I/O Supply voltage(for device with a nominal VDD of 2.5V for DDR266/333) I/O Supply voltage(for device with a nominal VDD of 2.6V for DDR400) I/O Reference voltage I/O Termination voltage(system) Input logic high voltage Input logic low voltage Input Voltage Level, CK and CK inputs Input Differential Voltage, CK and CK inputs V-I Matching: Pullup to Pulldown Current Ratio Input leakage current Output leakage current Output High Current(Normal strengh driver) ;VOUT = VTT + 0.84V Output High Current(Normal strengh driver) ;VOUT = VTT - 0.84V Output High Current(Half strengh driver) ;VOUT = VTT + 0.45V Output High Current(Half strengh driver) ;VOUT = VTT - 0.45V
Symbol
VDD VDD VDDQ VDDQ VREF VTT VIH(DC) VIL(DC) VIN(DC) VID(DC) VI(Ratio) II IOZ IOH IOL IOH IOL
Min
2.3 2.5 2.3 2.5 0.49*VDDQ VREF-0.04 VREF+0.15 -0.3 -0.3 0.36 0.71 -2 -5 -16.8 16.8 -9 9
Max
2.7 2.7 2.7 2.7 0.51*VDDQ VREF+0.04 VDDQ+0.3 VREF-0.15 VDDQ+0.3 VDDQ+0.6 1.4 2 5
Unit
V V V V V V V V V V uA uA mA mA mA mA
Note
1 2
3 4
Note : 1. VREF is expected to be equal to 0.5*VDDQ of the transmitting device, and to track variations in the dc level of same. Peak-to peak noise on VREF may not exceed +/-2% of the dc value. 2. VTT is not applied directly to the device. VTT is a system supply for signal termination resistors, is expected to be set equal to VREF, and must track variations in the DC level of VREF. 3. VID is the magnitude of the difference between the input level on CK and the input level on CK. 4. The ratio of the pullup current to the pulldown current is specified for the same temperature and voltage, over the entire temperature and voltage range, for device drain to source voltages from 0.25V to 1.0V. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. The full variation in the ratio of the maximum to minimum pullup and pulldown current will not exceed 1.7 for device drain to source voltages from 0.1 to 1.0.
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
9.0 DDR SDRAM IDD spec table
9.1 M470L3324BT(U)0 [ (32M x 64) 256MB Module ]
DDR SDRAM
(VDD=2.7V, T = 10C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) 660 760 20 120 100 220 400 920 1,120 1,060 20 12 1,800 500 620 20 120 100 120 200 780 860 1,000 20 12 1,620 440 560 20 120 80 120 200 680 760 960 20 12 1,440 440 560 20 120 80 120 200 680 760 960 20 12 1,440 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
9.2 M470L6524BT(U)0 [ (64M x 64) 512MB Module ]
(VDD=2.7V, T = 10C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) 1,060 1,160 40 240 200 440 800 1,320 1,520 1,460 40 24 2,200 700 820 40 240 200 240 400 980 1,060 1,200 40 24 1,820 640 760 40 240 160 240 400 880 960 1,160 40 24 1,640 640 760 40 240 160 240 400 880 960 1,160 40 24 1,640 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM
9.3 M470L2923BV0 [ (128M x 64) 1GB Module ]
(VDD=2.7V, T = 10C) Symbol IDD0 IDD1 IDD2P IDD2F IDD2Q IDD3P IDD3N IDD4R IDD4W IDD5 IDD6 Normal Low power IDD7A CC(DDR400@CL=3) B3(DDR333@CL=2.5) A2(DDR266@CL=2) B0(DDR266@CL=2.5) 2,080 2,240 80 480 400 560 1,520 2,360 2,680 2,880 80 48 4,200 1,400 1,600 80 480 400 480 800 1,840 1,880 2,400 80 48 3,520 1,280 1,480 80 480 400 480 800 1,600 1,640 2,320 80 48 3,120 1,280 1,480 80 480 400 480 800 1,600 1,640 2,320 80 48 3,120 Unit mA mA mA mA mA mA mA mA mA mA mA mA mA Optional Notes
* Module IDD was calculated on the basis of component IDD and can be differently measured according to DQ loading cap.
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
10.0 AC Operating Conditions
Parameter/Condition Input High (Logic 1) Voltage, DQ, DQS and DM signals Input Low (Logic 0) Voltage, DQ, DQS and DM signals. Input Differential Voltage, CK and CK inputs Input Crossing Point Voltage, CK and CK inputs Symbol VIH(AC) VIL(AC) VID(AC) VIX(AC) 0.7 0.5*VDDQ-0.2 Min VREF + 0.31 VREF - 0.31 VDDQ+0.6 Max
DDR SDRAM
Unit V V V V Note 3 3 1 2
0.5*VDDQ+0.2
Note : 1. VID is the magnitude of the difference between the input level on CK and the input on CK. 2. The value of VIX is expected to equal 0.5*VDDQ of the transmitting device and must track variations in the DC level of the same. 3. These parameters should be tested at the pim on actual components and may be checked at either the pin or the pad in simulation. the AC and DC input specificatims are refation to a Vref envelope that has been bandwidth limited 20MHz.
Vtt=0.5*VDDQ
RT=50 Output Z0=50 CLOAD=30pF VREF =0.5*VDDQ
Output Load Circuit (SSTL_2)
11.0 Input/Output Capacitance
Parameter Input capacitance(A0 ~ A12, BA0 ~ BA1,RAS,CAS,WE ) Input capacitance(CKE0,CKE1) Input capacitance( CS0, CS1) Input capacitance( CLK0, CLK1,CLK2) Input capacitance(DM0~DM7) Data & DQS input/output capacitance(DQ0~DQ63) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 Cout1 Min 41 34 34 25 6 6 Max 45 38 38 30 7 7 Min 49 42 42 25 6 6 Max 57 50 50 30 7 7
( TA= 25C, f=100MHz) M470L3324BT(U) M470L6524BT(U) M470L2923BN(V) Min 65 42 42 28 10 10 Max 81 50 50 34 12 12 Unit pF pF pF pF pF pF
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
12.0 AC Timming Parameters & Specifications
Parameter
Row cycle time Refresh row cycle time Row active time RAS to CAS delay Row precharge time Row active to Row active delay Write recovery time Last data in to Read command CL=2.0 Clock cycle time Clock high level width Clock low level width DQS-out access time from CK/CK Output data access time from CK/CK Data strobe edge to ouput data edge Read Preamble Read Postamble CK to valid DQS-in DQS-in setup time DQS-in hold time DQS falling edge to CK rising-setup time DQS falling edge from CK rising-hold time DQS-in high level width DQS-in low level width Address and Control Input setup time(fast) Address and Control Input hold time(fast) Address and Control Input setup Address and Control Input hold time(slow) Data-out high impedence time from CK/CK Data-out low impedence time from CK/CK Mode register set cycle time DQ & DM setup time to DQS DQ & DM hold time to DQS Control & Address input pulse width DQ & DM input pulse width Exit self refresh to non-Read command Exit self refresh to read command Refresh interval time Output DQS valid window Clock half period Data hold skew factor DQS write postamble time Active to Read with Auto precharge command Autoprecharge write recovery + Precharge time CL=2.5 CL=3.0 tCH tCL tDQSCK tAC tDQSQ tRPRE tRPST tDQSS tWPRES tWPRE tDSS tDSH tDQSH tDQSL tIS tIH tIS tIH tHZ tLZ tMRD tDS tDH tIPW tDIPW tXSNR tXSRD tREFI tQH tHP tQHS tWPST tRAP tDAL 0.4 15 (tWR/tCK) + (tRP/tCK) tHP -tQHS tCLmin or tCHmin tCK
DDR SDRAM
Symbol
tRC tRFC tRAS tRCD tRP tRRD tWR tWTR
CC B3 A2 B0 (DDR400@CL=3.0) (DDR333@CL=2.5) (DDR266@CL=2.0) (DDR266@CL=2.5) Unit Min Max Min Max Min Max Min Max
55 70 40 15 15 10 15 2 6 5 0.45 0.45 -0.55 -0.65 0.9 0.4 0.72 0 0.25 0.2 0.2 0.35 0.35 0.6 0.6 0.7 0.7 -0.65 -0.65 10 0.4 0.4 2.2 1.75 75 200 7.8 0.5 0.6 0.4 18 (tWR/tCK) + (tRP/tCK) tHP -tQHS tCLmin or tCHmin +0.65 +0.65 12 10 0.55 0.55 +0.55 +0.65 0.4 1.1 0.6 1.28 70K 60 72 42 18 18 12 15 1 7.5 6 0.45 0.45 -0.6 -0.7 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.75 0.75 0.8 0.8 -0.7 -0.7 12 0.45 0.45 2.2 1.75 75 200 7.8 0.55 0.6 0.4 20 (tWR/tCK) + (tRP/tCK) tHP -tQHS tCLmin or tCHmin +0.7 +0.7 12 12 0.55 0.55 +0.6 +0.7 0.45 1.1 0.6 1.25 70K 65 75 45 20 20 15 15 1 7.5 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 1.0 1.0 -0.75 -0.75 15 0.5 0.5 2.2 1.75 75 200 7.8 0.75 0.6 0.4 20 (tWR/tCK) + (tRP/tCK) tCK tHP -tQHS tCLmin or tCHmin +0.75 +0.75 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 70K 65 75 45 20 20 15 15 1 10 7.5 0.45 0.45 -0.75 -0.75 0.9 0.4 0.75 0 0.25 0.2 0.2 0.35 0.35 0.9 0.9 1.0 1.0 -0.75 -0.75 15 0.5 0.5 2.2 1.75 75 200 7.8 0.75 0.6 +0.75 +0.75 12 12 0.55 0.55 +0.75 +0.75 0.5 1.1 0.6 1.25 tCK tCK ns ns ns tCK tCK tCK ns tCK tCK tCK tCK tCK ns ns ns ns ns ns ns ns ns ns ns ns tCK us ns ns ns tCK 70K ns ns ns ns ns ns ns tCK ns ns
Note
22
13
15, 17~19 15, 17~19
16~19 16~19 11 11 j, k j, k 18 18
14 21 20, 21 21 12
23
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
13.0 System Characteristics for DDR SDRAM
DDR SDRAM
The following specification parameters are required in systems using DDR333, DDR266 devices to ensure proper system performance. these characteristics are for system simulation purposes and are guaranteed by design. Table 1 : Input Slew Rate for DQ, DQS, and DM
AC CHARACTERISTICS PARAMETER DQ/DM/DQS input slew rate measured between VIH(DC), VIL(DC) and VIL(DC), VIH(DC) SYMBOL DCSLEW DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD Units V/ns Notes a, m
Table 2 : Input Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tIS 0 +50 +100 tIH 0 0 0 Units ps ps ps Notes i i i
Table 3 : Input/Output Setup & Hold Time Derating for Slew Rate
Input Slew Rate 0.5 V/ns 0.4 V/ns 0.3 V/ns tDS 0 +75 +150 tDH 0 +75 +150 Units ps ps ps Notes k k k
Table 4 : Input/Output Setup & Hold Derating for Rise/Fall Delta Slew Rate
Delta Slew Rate +/- 0.0 V/ns +/- 0.25 V/ns +/- 0.5 V/ns tDS 0 +50 +100 tDH 0 +50 +100 Units ps ps ps Notes j j j
Table 5 : Output Slew Rate Characteristice (X4, X8 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 1.0 1.0 Maximum (V/ns) 4.5 4.5 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 6 : Output Slew Rate Characteristice (X16 Devices only)
Slew Rate Characteristic Pullup Slew Rate Pulldown slew Typical Range (V/ns) 1.2 ~ 2.5 1.2 ~ 2.5 Minimum (V/ns) 0.7 0.7 Maximum (V/ns) 5.0 5.0 Notes a,c,d,f,g,h b,c,d,f,g,h
Table 7 : Output Slew Rate Matching Ratio Characteristics
AC CHARACTERISTICS PARAMETER Output Slew Rate Matching Ratio (Pullup to Pulldown) DDR333 MIN TBD MAX TBD DDR266 MIN TBD MAX TBD Notes e,m
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
14.0 Component Notes
DDR SDRAM
1. All voltages referenced to Vss. 2. Tests for ac timing, IDD, and electrical, ac and dc characteristics, may be conducted at nominal reference/supply voltage levels, but the related specifications and device operation are guaranteed for the full voltage range specified. 3. Figure 1 represents the timing reference load used in defining the relevant timing parameters of the part. It is not intended to be either a precise representation of the typical system environment nor a depiction of the actual load presented by a production tester. System designers will use IBIS or other simulation tools to correlate the timing reference load to a system environment. Manufacturers will correlate to their production test conditions (generally a coaxial transmission line terminated at the tester electronics). VDDQ 50 Output (Vout) 30pF
Figure 1 : Timing Reference Load
4. AC timing and IDD tests may use a VIL to VIH swing of up to 1.5 V in the test environment, but input timing is still referenced to VREF (or to the crossing point for CK/CK), and parameter specifications are guaranteed for the specified ac input levels under normal use conditions. The minimum slew rate for the input signals is 1 V/ns in the range between VIL(ac) and VIH(ac). 5. The ac and dc input level specifications are as defined in the SSTL_2 Standard (i.e., the receiver will effectively switch as a result of the signal crossing the ac input level and will remain in that state as long as the signal does not ring back above (below) the dc input LOW (HIGH) level. 6. Inputs are not recognized as valid until VREF stabilizes. Exception: during the period before VREF stabilizes, CKE 0.2VDDQ is recognized as LOW. 7. Enables on.chip refresh and address counters. 8. IDD specifications are tested after the device is properly initialized. 9. The CK/CK input reference level (for timing referenced to CK/CK) is the point at which CK and CK cross; the input reference level for signals other than CK/CK, is VREF. 10. The output timing reference voltage level is VTT. 11. tHZ and tLZ transitions occur in the same access time windows as valid data transitions. These parameters are not referenced to a specific voltage level but specify when the device output is no longer driving (HZ), or begins driving (LZ). 12. The maximum limit for this parameter is not a device limit. The device will operate with a greater value for this parameter, but sys tem performance (bus turnaround) will degrade accordingly. 13. The specific requirement is that DQS be valid (HIGH, LOW, or at some point on a valid transition) on or before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. when no writes were previ ously in progress on the bus, DQS will be tran sitioning from High- Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on tDQSS. 14. A maximum of eight AUTO REFRESH commands can be posted to any given DDR SDRAM device. 15. For command/address input slew rate 1.0 V/ns 16. For command/address input slew rate 0.5 V/ns and < 1.0 V/ns 17. For CK & CK slew rate 1.0 V/ns 18. These parameters guarantee device timing, but they are not necessarily tested on each device. They may be guaranteed by device design or tester correlation. 19. Slew Rate is measured between VOH(ac) and VOL(ac). 20. Min (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can be greater than the minimum specification limits for tCL and tCH).....For example, tCL and tCH are = 50% of the period, less the half period jitter (tJIT(HP)) of the clock source, and less the half period jitter due to crosstalk (tJIT(crosstalk)) into the clock traces. 21. tQH = tHP - tQHS, where: tHP = minimum half clock period for any given cycle and is defined by clock high or clock low (tCH, tCL). tQHS accounts for 1) The pulse duration distortion of on-chip clock circuits; and 2) The worst case push-out of DQS on one tansition followed by the worst case pull-in of DQ on the next transition, both of which are, separately, due to data pin skew and output pattern effects, and p channel to n-channel variation of the output drivers. 22. tDQSQ - Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers for any given cycle. 23. tDAL = (tWR/tCK) + (tRP/tCK) For each of the terms above, if not already an integer, round to the next highest integer. Example: For DDR266B at CL=2.5 and tCK=7.5ns tDAL = (15 ns / 7.5 ns) + (20 ns/ 7.5ns) = (2) + (3) tDAL = 5 clocks
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
15.0 System Notes:
a. Pullup slew rate is characteristized under the test conditions as shown in Figure 2.
DDR SDRAM
Test point Output 50 VSSQ Figure 2 : Pullup slew rate test load
b. Pulldown slew rate is measured under the test conditions shown in Figure 3.
VDDQ 50 Output Test point Figure 3 : Pulldown slew rate test load
c. Pullup slew rate is measured between (VDDQ/2 - 320 mV +/- 250 mV) Pulldown slew rate is measured between (VDDQ/2 + 320 mV +/- 250 mV) Pullup and Pulldown slew rate conditions are to be met for any pattern of data, including all outputs switching and only one output switching. Example : For typical slew rate, DQ0 is switching For minmum slew rate, all DQ bits are switching from either high to low, or low to high. The remaining DQ bits remain the same as for previous state. d. Evaluation conditions Typical : 25 C (T Ambient), VDDQ = 2.5V(for DDR266/333) and 2.6V(for DDR400), typical process Minimum : 70 C (T Ambient), VDDQ = 2.3V(for DDR266/333) and 2.5V(for DDR400), slow - slow process Maximum : 0 C (T Ambient), VDDQ = 2.7V(for DDR266/333) and 2.7V(for DDR400), fast - fast process e. The ratio of pullup slew rate to pulldown slew rate is specified for the same temperature and voltage, over the entire temperature and voltage range. For a given output, it represents the maximum difference between pullup and pulldown drivers due to process variation. f. Verified under typical conditions for qualification purposes. g. TSOPII package divices only. h. Only intended for operation up to 266 Mbps per pin. i. A derating factor will be used to increase tIS and tIH in the case where the input slew rate is below 0.5V/ns as shown in Table 2. The Input slew rate is based on the lesser of the slew rates detemined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. j. A derating factor will be used to increase tDS and tDH in the case where DQ, DM, and DQS slew rates differ, as shown in Tables 3 & 4. Input slew rate is based on the larger of AC-AC delta rise, fall rate and DC-DC delta rise, Input slew rate is based on the lesser of the slew rates determined by either VIH(AC) to VIL(AC) or VIH(DC) to VIL(DC), similarly for rising transitions. The delta rise/fall rate is calculated as: {1/(Slew Rate1)} - {1/(Slew Rate2)} For example : If Slew Rate 1 is 0.5 V/ns and slew Rate 2 is 0.4 V/ns, then the delta rise, fall rate is - 0.5ns/V . Using the table given, this would result in the need for an increase in tDS and tDH of 100 ps. k. Table 3 is used to increase tDS and tDH in the case where the I/O slew rate is below 0.5 V/ns. The I/O slew rate is based on the lesser on the lesser of the AC - AC slew rate and the DC- DC slew rate. The inut slew rate is based on the lesser of the slew rates deter mined by either VIH(ac) to VIL(ac) or VIH(DC) to VIL(DC), and similarly for rising transitions. m. DQS, DM, and DQ input slew rate is specified to prevent double clocking of data and preserve setup and hold times. Signal transi tions through the DC region must be monotonic.
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
16.0 Command Truth Table
COMMAND Register Register Extended MRS Mode Register Set Auto Refresh Refresh Entry Self Refresh Exit CKEn-1 H H H L H H H H All Banks Entry Exit Entry Precharge Power Down Mode Exit DM No operation (NOP) : Not defined L H H X H L H H H L H CKEn X X H L H X X X X X L H L CS L L L L H L L L L L H L X H L H L RAS L L L H X L H H H L X V X X H X V X X H X H X H
DDR SDRAM
(V=Valid, X=Dont Care, H=Logic High, L=Logic Low) CAS L L L H X H L L H H X V X X H X V WE BA0,1 A10/AP L L H H X H H L L L X V X X H X V X X 8 9 9 X X V X L H V V V A0 ~ A9 A11, A12 Note 1, 2 1, 2 3 3 3 3
OP CODE OP CODE X X Row Address (A0~A9, A11,A12) L H L H X X Column Address Column Address
Bank Active & Row Addr. Read & Column Address Write & Column Address Auto Precharge Disable Auto Precharge Enable Auto Precharge Disable Auto Precharge Enable Bank Selection
4 4 4 4, 6 7 5
Burst Stop Precharge
Active Power Down
Note : 1. OP Code : Operand Code. A0 ~ A12 & BA0 ~ BA1 : Program keys. (@EMRS/MRS) 2. EMRS/ MRS can be issued only at all banks precharge state. A new command can be issued 2 clock cycles after EMRS or MRS. 3. Auto refresh functions are same as the CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. 5. If A10/AP is "High" at row precharge, BA0 and BA1 are ignored and all banks are selected. 6. During burst write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 7. Burst stop command is valid at every burst length. 8. DM sampled at the rising and falling edges of the DQS and Data-in are masked at the both edges (Write DM latency is 0). 9. This combination is not defined for any function, which means "No Operation(NOP)" in DDR SDRAM.
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
17.0 Physical Dimensions
17.1 32M x 64 (M470L3324BT(U))
DDR SDRAM
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00)
Full R 2.0
1
39 41
199
0.086 2.15
0.456 11.40
0.07 (1.8+/-0.1) 0.098 2.45
2
0.17 (4.20) 0.096 (2.40+/-0.1)
Z
1.896 (47.40)
2- 0.07 (1.8+0.1/-0.0)
Y
40 42
200
(4.00 Min)
(4.00 Min)
0.157 Min
0.157 Min
0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 )
0.150 Max (3.80 Max)
0.102 Min
1.25 (31.75) 0.018 0.001 0.01 (0.2+/-0.15) 0.024 TYP (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 32Mx16 SDRAM, TSOPII SDRAM Part No. : K4H511638B
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM
17.2 64Mx64 (M470L6524BT(U))
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00)
Full R 2.0
1
39 41
199
0.086 2.15
0.456 11.40
0.07 (1.8+/-0.1) 0.098 2.45
2
0.17 (4.20) 0.096 (2.40+/-0.1)
Z
1.896 (47.40)
2- 0.07 (1.8+0.1/-0.0)
Y
40 42
200
(4.00 Min)
(4.00 Min)
0.157 Min
0.157 Min
0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 )
0.150 Max (3.80 Max)
0.102 Min
1.25 (31.75) 0.018 0.001 0.01 (0.2+/-0.15) 0.024 TYP (0.60 TYP)
0.04 0.0039 (1.00 0.10)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 32Mx16 SDRAM, TSOPII SDRAM Part No. : K4H511638B
Rev. 1.5 June 2005
256MB, 512MB, 1GB Unbuffered SODIMM
DDR SDRAM
17.3 128Mx64 (M4702923BN(V))
Units : Inches (Millimeters)
2.70 (67.60) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00)
Full R 2x
1
39 41
199
0.086 2.15
0.456 11.40
0.07 (1.8) 0.098 2.45
2 40 42
0.17 (4.20) 0.096 (2.40)
Z
1.896 (47.40)
2- 0.07 (1.80)
Y
200
0.150 Max (3.80 Max) (4.00 Min) (4.00 Min) 0.157 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.04 0.0039 (1.00 0.1)
(2.55 Min)
0.102 Min
0.04 0.0039 (1.00 0.10)
0.024 TYP (0.60 TYP)
Detail Z
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 64Mx8 DDR SDRAM, sTSOPII-300mil SDRAM Part No. : K4H510838B
Rev. 1.5 June 2005
1.25 (31.75) 0.018 0.001 (0.45 0.03) 0.008 3/4 0.006 (0.20 3/4 0.15 )

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